http://www.timing-diagrams.com/dokuwiki/ 2010-08-17T21:33:32-06:00 http://www.timing-diagrams.com/dokuwiki/ http://www.timing-diagrams.com/dokuwiki/lib/images/favicon.ico text/html 2009-08-11T18:07:08-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=contact&rev=1250035628&do=diff Contact Author Feel free to email and make suggestions for new features and improvements, report problems, or discuss the future plans for the program. Dan Fabrizio <timinganalyzer@gmail.com> text/html 2010-04-01T19:22:02-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=download&rev=1270171322&do=diff Release Notes Version 0.949 Download Beta Version 0.949 * testing fix for end time set to 0.0 in .tim file. A message dialog appears if the end time is set 0.0 when saving and aborts the save so you can change the end time. You can change the end time from the edit menu. The default value is 1600. If you saved the diagram with one of the previous versions, this could have occurred. If you run into this problem with this version, please let me know and if possible, trace your last few st… text/html 2010-02-06T20:44:26-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=features&rev=1265514266&do=diff Current Features * Generate timing diagrams directly from VHDL or Verilog Simulations. * Generate timing diagrams directly from VCD files. * Easily draw and edit timing diagrams. * Easily add pulses with one mouse click. * Easily add pulses synchronized to any clock in any signal or bus * Easily add automatically incrementing and decrementing pulses. * Undo / Redo * Timing analysis with minimum, typical, maximum, and min-max delay margins. * User defined delays and const… text/html 2009-10-09T16:39:10-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=future_plans&rev=1255127950&do=diff Possible New Direction I'm changing to Python for the scripting language. I'm also considering converting the TimingAnalyzer from Java to Python with mostly a scripting interface. With scripts, you can quickly build complex timing diagrams, do timing analysis, create testbenches, generate test vectors from waveform diagrams, and create timing diagrams from simulation VCD files. text/html 2010-03-20T22:59:10-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=getting_started&rev=1269147550&do=diff Installing the TimingAnalyzer * Download and install the JRE Version 1.6.0 or newer if needed. * Download the zip file. * Unzip the downloaded TimingAnalyzer_bxx.zip in any directory. c:\Apps\TimingAnalyzer_bxx dir TimingAnalyzer.jar -- The executable program docs dir -- html help files required by program images dir -- images required by program scripts dir -- user scripts themes dir … text/html 2010-08-16T20:22:48-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=introduction&rev=1282011768&do=diff Timing Analyzer The TimingAnalyzer can be used to easily draw timing diagrams and perform timing analysis to find faults in digital logic systems. The diagrams can be saved in many different image file formats and scalable vector formats so they can easily be added to technical documentation such as specifications, data sheets, technical manuals, and presentations. The diagrams are saved as simple text files that can be easily distributed to other users. text/html 2010-02-27T21:30:21-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=issues&rev=1267331421&do=diff New Feature List * add analog signals * generate constraints in standard formats like SDC, UCF * add RC delays as option in pulse panel. Used for tri-state outputs that connect to pull-up or pull-down * save and edit transactions. For example: save and edit read and write cycles that can be copied,cut, and pasted quickly so its easy to make large diagrams from a sequence of transactions. text/html 2009-10-25T12:20:04-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=license&rev=1256494804&do=diff The TimingAnalyzer License The program is free to use by anyone without any limitations. The TimingAnalyzer is being distributed as Freeware. No warranties or guarantees are provided by the author of the program. If you decide to use the program, you should be aware that it is a work in progress and it is not be bug free. Bugs reported to author will be fixed as soon as possible. text/html 2010-08-16T20:49:37-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=news&rev=1282013377&do=diff Latest News Beta Version 0.950 Coming Soon (8/16/10) New Features: * edge margins now can be defined without the need of adding a delay. You easily set and edit min and max times for any edge. This can be used for jitter or uncertainty or just to show the time it takes for new state to go stable. * min and max edges can be edited any time even when margins are displayed. * X states are filled in gray just like margins. text/html 2009-08-21T19:28:34-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=screenshots&rev=1250904514&do=diff Images TimingAnalyzer running in Ubuntu Linux Click in Image to show the full size picture. Videos Moving Transactions Synchronously Moving transactions synchronously can make life much easier when you decide for example to add a read cycle in between two write cycles. So you want to move the 2nd write cycle over maybe 10 clock cycles. This is done with synchronous moves. Simply select the 2nd write cycle by dragging the mouse around the transaction, then use Alt and Right Key combi… text/html 2009-07-15T19:09:36-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=scripting&rev=1247706576&do=diff Scripting Basics The user can write and develop Java like scripts and soon Python scripts to add new features or functions to the TimingAnalyzer. The scripts are executed while the program is running. Use any text editor to write the scripts and store them in the scripts directory. Select “Script” from the file menu, a dialog listing all the scripts is displayed. Choose the script and hit the “Execute” button. It's best to start the TimingAnalyzer from the command line when developing and … text/html 2010-02-27T08:51:52-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=sidebar&rev=1267285912&do=diff * Introduction * Latest News * Features * Screenshots and Videos * Getting Started * Step by Step Examples * Scripting * Documentation * Application Notes * Download * ToDo, Issues, New Features * Contact * License text/html 2009-07-25T10:38:19-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=step_by_step_examples&rev=1248539899&do=diff Memory Read Timing Analysis * Open the file cnstrnt_err.tim in the examples dir. The diagram shows a 16 bit address bus, chip select (CS), an 8 bit data bus (DATA[7:0], and a control signal RDY. In State S1, the address becomes valid after tclkadd delay. CS goes active after tpd delay. Data becomes valid after the access time of the memory, tacc. text/html 2010-02-11T18:58:41-06:00 http://www.timing-diagrams.com/dokuwiki/doku.php?id=user_feedback&rev=1265939921&do=diff User Suggestions for New Features and Improvements The lists below summarize the suggestions that were received from users. If you don't see a suggestion you made, please let me know. GUI Related * Delay and Constraint visibility. Add right click pop-up menu item to display or hide them. * Import and Export Constraints and Delays in Spreadsheet csv format. * Have option to show the actual time of a pulse width labels * Add a sidebar that lists all the selectable objects * All…