1. Open the file cnstrnt_err.tim in the examples dir.

The diagram shows a 16 bit address bus, chip select (CS), an 8 bit data bus (DATA[7:0], and a control signal RDY. In State S1, the address becomes valid after tclkadd delay. CS goes active after tpd delay. Data becomes valid after the access time of the memory, tacc.

It is required that the data is valid for the setup time of 12nS as shown in the tsetup constraint.

1. File Menu > New or Ctrl-n. Start a new timing diagram.
2. Add Menu > Add Clock or Ctrl-1. Add the CLOCK.
3. Add Menu > Add Bus or Ctrl-3. Add the ADD bus.
4. Add Menu > Add Signal or Ctrl-2. Add CS*.
5. Add Menu > Add Bus or Ctrl-3. Add the DATA bus.
6. Add Menu > Add Signal or Ctrl-2. Add the RDY* signal.

1. Add Menu → Pusle or Ctrl-9. Set “Auto Increment” equal to 0. Set signal value to FFC0.
2. Click in ADD bus at 30ns,50ns, and 70nS. This will make a FFC0 pulse for 3 clock cycles.
3. Select “L”. Click in CS* at 50nS and 70nS. This will make a low pulse for 2 clock cycles.
4. Change signal value to 55. Click in DATA bus at 70nS. This will make a 55 pulse for 1 clock cycle.
5. Select “L”. Click in RDY* at 70nS. This will make a low pulse for 1 clock cycle.

Click in delay and contraint labels in diagram and then use the arrow key combinations to position the label.

1. Select 1st rising edge of CLOCK. Select 1st edge of ADD.
2. Add Menu > User Delay or Ctrl-7. Add delay tclk2add.
3. Select 1st edge of ADD and 1st edge of CS*. Add delay tpd.
4. Select 1st edge of CS* and 1st edge of DATA. Add delay tacc.
5. Select 1st edge of DATA and 4th rising edge of CLOCK.
6. Add Menu > User Constraint or Ctrl-8. Add constraint tsetup.
7. Select 4th rising edge of CLOCK and 2nd edge of ADD. Add delay tclk2q.
8. Select 4th rising edge of CLOCK and 2nd edge of CS*. Add delay tclk2q from pop-up menu “Add Used Delay”.
9. Select 4th rising edge of CLOCK and 2nd edge of DATA. Add delay tclk2q from pop-up menu “Add Used Delay”.
10. Select 4th rising edge of CLOCK and 2nd edge of RDY*. Add delay tclk2q from pop-up menu “Add Used Delay”.

1. Select 1st rising edge of CLOCK. Add Menu > StateBar (ctrl-4). Add StateBar S1 using dialog.
2. Select 2nd rising edge of CLOCK. Add StateBar S2 using dialog already open.
3. Select 3nd rising edge of CLOCK. Add StateBar S3 using dialog already open.
4. Select 4nd rising edge of CLOCK. Add StateBar S1 using dialog already open.

Use the timing analysis min, typ, and max menus to see delays for each case. Set timing analysis margins to check for a constraint violation. You could increase the CLOCK frequency or change any of the delays to quickly check to see if the interface meets timing at faster clock rates with slower parts.

Open the file xilinx_ddr_sep.tim in the examples dir. The diagram above shows this file. This is the timing diagram for the Xilinx Input DDR set to SAME_EDGE_PIPELINED mode.

The diagram shows the clock C, the clock enable CE, the register D inputs, and the register outputs Q1 and Q2. As you can see from the diagram, the D input changes every half clock cycle. One input register clocks the D input on the rising edge of the clock, and the other register clocks the D input on the falling edge of the clock. You can also see that the outputs change one clock cycle later because of the pipeline stage.

1. File Menu > New or Ctrl-n. Start a new timing diagram.
2. Add Menu > Add Clock or Ctrl-1. Add C.
3. Add Menu > Add Signals or Ctrl-2. Add CE, D, Q1, and Q2.

1. Add Menu - Pulse or Ctrl 9. Select “H”. Click in CE 8 times just after each rising edge of C. This will make CE “H” for 8 C clock cycles. Select 1st edge. Drag to 2.5nS.
2. Set signal value to DA0. Click “Synchronize Rising and Falling Edge” button. Click in D after each edge to add the incrementing values.
3. Set the pulse offset to 2.5nS. Set the signal value to DA0.
4. Set the “Auto Inc by” value to 2. Select “Synchronize to Rising Edge”
5. Click in Q1 after each rising edge of C to add values that increment by 2.
6. Set the signal value to DA1. Click in Q2 after each rising edge of C to add values that increment by 2.

1. Select 1st rising edge of C. Add Menu → StateBar or Ctrl-4. Set the “NO LABEL” in the “New State Label” combobox. Set “Line Type” to Dashed. Click Add.
2. Select 2nd rising edge of C. Use already open StateBar dialog. Just click “Add”.
3. Repeat last step for each positive edge in C.

The diagram above shows the timing diagram for output DDR registers found in the OLOGIC block of the Xilinx Virtex 4 FPGA. Input data on D1 and D2 changes once per CLK period and the output data on Q1 changes every half cycle. This document describes how to use the “TimingAnalyzer” to quickly draw this diagram. Beta version 0.91 is required to follow this example.

1. Start New Diagram. Ctrl-n.
2. Add Clock CLK. Ctrl-1, CLK 100MHZ 50% 1ns 1ns H, click “Add” button.
3. Add Signal CE. Ctrl-2, CE 1ns 1ns L, click the “Add” button.
4. Add Signal D1. D1 1ns 1ns D10, click “Add” button.
5. Add Signal D2. D2 1ns 1ns D20, click “Add” button.
6. Add Signal Q1. Q1 1ns 1ns X, click “Add” button.
7. Add High Pulses to CE. Ctrl-9. H button, click in CE once per clock cycle to add incrementing values.
8. Add Incrementing Pulses to D1. D11 in entry, Rising Edge Sync button, Increment by 1, click in D1 once per clock cycle to add incrementing values.
9. Add Incrementing Pulses to D2. D21 in Next State entry, click in D2 once per clock cycle to adding incrementing values.
10. Add Output Pulses to Q1. D11 in Next State entry, Rising Edge Sync button , click in Q1 once per clock cycle to add incrementing values. D21 in Next State entry, Both Edge Sync button, click in Q1 after every clock negative edge to add incrementing values.
11. Position First Edge in CE. Select edge, move left 2 times with left arrow key.
12. Position Pulses in D1. Select first edge, select all edges to the right, move all the edges left 2 times with left arrow key.
13. Position Pulses in D2. Select first edge, select all edges to the right, move all the edges right 2 times with right arrow key.
14. Position Pulses in Q1. Select first edge, select all edges to the right, move all the edges right 2 times with right arrow key.

• Step 1. Start a new timing diagram. You can use the File → new menu or Ctrl-n keystroke shortcut.
• Step 2. Add CLK. Use the Add → DigitalClock menu or the Ctrl-1 keystroke shortcut. The clock panel is displayed on the left of the diagram. To add a clock, just fill in the required parameters and click the “Add” button. In this case, we want the name to be CLK, a 100 MHZ frequency, 50% duty cycle, 1 ns rise and fall times, and a HIGH start state.
• Steps 3-6. Add CE, D1, D2, and Q1. Use the Add → DigitalSignal menu or the Ctrl 2 keystroke shortcut. The signal panel is displayed on the left of the diagram. To add the signal, fill in the required parameters and click the “Add” button. For CE, we want the name to be CE, 1 ns rise and fall times, and a LOW start state. For D1, we want the name to be D1 and the start state set to D10. For D2, we want the name to be D2 and the start state set to D20. For Q1, we want the name to be Q1 and the start state set to X.
• Step 7. Add H pulses to CE. Use the Add → Pulse menu or Ctrl-9 keystroke shortcut. Click the H button or use the h key. This sets the next state to HIGH. Click in the CE signal anytime during the 2nd clock cycle to add a H pulse during that cycle. Continue to click in the CE signal one time in each of the next 5 clock cycles to extend the H pulse.
• Step 8. Add pulses to D1. Enter D11 in the signal value entry. Verify the “Rising Edge Synchronized” button is selected. This is the button with the up arrow. Verify the “Increment by” input is set to 1. Click in the D1 signal anytime during the 2nd clock cycle to add the D11 pulse. Notice the next state value changed to D12. Click in the next clock cycle to add the D12 pulse. Click in each of the 4 next clock cycles until D16 is added.
• Step 9. Add pulses to D2. Enter D21 in the signal value entry. Verify the “Rising Edge Synchronized” button is selected. This is the button with the up arrow. Verify the “Increment by” input is set to 1. Click in the D2 signal anytime during the 2nd clock cycle to add the D21 pulse. Notice the next state value changed to D22. Click in the next clock cycle to add the D22 pulse. Click in each of the 4 next clock cycles until D26 is added.
• Step 10. Add pulses to Q1. Repeat step 5. Now we will add the pulses that occur on the falling edge of the clock. Enter D21 in the signal value entry. Click “Synchronize to Rising and Falling Edges” button. Click in Q1 after each clock negative edge to add the incrementing values D21 to D25.
• Steps 11-14. The last steps are needed to position the pulses correctly in each signal. This is commonly done by selecting the first edge you want to move. Next, right click to bring up the pop-up menu and “select all edges right”. Now you can move all the pulses at one time by dragging the mouse or using the the shift or alt and left / right key combinations. These steps are not needed if offset times of +/- 2ns where used when adding the pulses in steps 7-10.