New Features:

• edge margins now can be defined without the need of adding a delay. You easily set and edit min and max times for any edge. This can be used for jitter or uncertainty or just to show the time it takes for new state to go stable.
• min and max edges can be edited any time even when margins are displayed.
• X states are filled in gray just like margins.

Three new user forums have been added to the website. GUI Help Forum, Scripting Help Forum, and Requests for New Features and Improvements Forum.

A new source code repository for the Python scripts that are distributed with the TimingAnalyzer has been started at google code. An effort is in progress to develop python libraries and scripts that can be used to extend the TimingAnalyzer with Python plugins.

The newest feature is ability to read VCD files and convert it to a timing diagram automatically. I have tested with Xilinx Chipscope and Modelsim VCD files. Modelsim VCD files don't seem to contain buses so I added a function, “Bus Signals” to make buses from sequentially ordered signals like ADIO<31>, ADIO<30>, ADIO<29> … You have to hold the shift key and click on each signal to select multiple signals. Better signal group selections will be addressed in the next version. Selecting groups of signals will only take 2 clicks.

Refer to the documentation for more information

This app note shows how to use Verilog to generate timing diagrams by writing text files which are Python scripts that the TimingAnalyzer executes to draw the diagram. A separate module in the example, sram_timing_diagram.v, includes all the source code use to generate the Python script. You can read it and download the example at: Generate Timing Diagrams from Verilog Simulations

A separate component, sram_timing_diagram.vhd, is now used to generate the timing diagram Python script. Start and end time are specified as generic parameters so you can make timing diagrams of any window in time from the simulation. This could be used as a template and modified to generate timing diagrams for any interface. A python script could developed that automatically builds this file for given list of signals, anyone interested?

With Beta 0.945, you can build timing diagrams directly from RTL. Generate Timing Diagrams from VHDL Simulations You can quickly build many timing diagrams with Python scripts that are automatically generated during simulations.

With Beta 0.944, a new button on the toolbar will zoom in completely and show the entire timing diagram. If you drag the mouse horizontally while holding down the shift key, you expand that window in time or zoom in to a certain part of the timing diagram. The logic functions defined to this point can be used in Python scripts.

With Beta 0.943, Buffer and Inverter logic simulation functions have been added. tphl and tplh delays are optional. Also, a new scripting function zoomIn(startTime,endTime) allows the user to zoomIn to certain areas on the timing diagram. New functions, “Zoom Full” and “Zoom Between” will be added to the GUI soon with buttons on the toolbar.

With Beta 0.941, the first two of many logic simulation functions have been added, the DFF and Binary Counter. These are real synchronous logic simulations that get executed when the function is added. Optional settings for the DFF allow you to specify rising edge or falling edge triggered, with or without RST, PRE, and EN inputs. Optional settings for counters let you specify up or down counters, rising or falling edge triggered, parallel loads, RST, PRE, and EN inputs.

Keep checking the website for new versions coming soon with more logic functions. Feel free to request functions you would like to see added.