The most common way to draw timing diagrams is by using the Graphical User Interface (GUI). There are example timing diagrams in the examples directory and there are also step-by-step examples on this website. You can draw timing diagrams using Python or Java scripts. There are examples of both Python and Java scripts in the scripts directory and or follow the scripting tutorial.

The basic procedure for drawing a diagram is:

1. Add a Clock.
2. Add other signals below the clock. These signals are synchronized to the clock above.
3. Add pulses that are synchronized to the clock above in the signals. Click in the signal during a clock cycle with the next state set in the Pulse Panel.
   1. Use “Rising Edge” is the signal represents the output from a Rising Edge Clocked FF.
   2. Use “Falling Edge” if the signal represents the output from a falling Edge Clocked FF.
   3. Use “Rising and Falling Edge” if the signal represents the output from a DDR.

The pulses that have been added are not connected to the clock signal. So if you change the frequency of the clock signal, the pulses in the signals will not adjust to the new position of the clock edges. When the pulses were added, the clock cycle time was used in order to calculate the time of the edges in the pulses. In order to have the pulse edge times follow any change in frequency of the synchronizing clock, you have add Delays between Clock Edges and Edges in the Pulses. Delays represent actual hardware delays like combinatorial delays tphl or tplh or tcomb, as well as synchronous delays like register CLK-to-Q output delays.