The TimingAnalyzer can be used to easily draw timing diagrams and perform timing analysis to find faults in digital logic systems. The diagrams can be saved in many different image file formats and scalable vector formats so they can easily be added to technical documentation such as specifications, data sheets, technical manuals, and presentations. The diagrams are saved as simple text files that can be easily distributed to other users.
With Python scripts, you can customize the program or use the included scripts to draw large complex timing diagrams quickly, generate test vectors for analog and digital simulations, build test-benches, or add new features to the program.
I use the program to draw timing diagrams during the design cycle to help visualize the logic functions needed for a digital system. Using the logic simulation functions, you can quickly add commonly used synchronous and combinatorial logic functions to simplify drawing more complex diagrams. During verification, I use it to document simulation results using the methods described in the application note Generate Timing Diagrams from VHDL Simulations
Written in Java, it runs on any platform that supports the Java Run-time Environment, JRE1.6.0 or Java Development Kit JDK1.6.0 or newer. I hope you find it useful and helpful for your projects.
Regards, Dan Fabrizio