Using the TimingAnalyzer, you can quickly draw timing diagrams and build libraries of timing diagrams. Using the built-in analysis functions, you can quickly find speed related design issues since setup and hold violations are detected, reported, and shown in the diagrams.
You can draw the diagrams using the GUI or Python scripts. Timing diagrams can be created automatically from simulation VCD files so they can be annotated and used in documenation. Application notes included in the documentation desribe how to create Verilog or VHDL monitors that automatically generate timing diagrams.