The TimingAnalyzer (TA)¶
Using the TimingAnalyzer, you can quickly draw timing diagrams, build libraries of timing diagrams, and perform timing analysis on logic designs. Using the built-in timing analysis functions, reported setup and hold violations indicate logic design problems.
You can draw timing diagrams using the GUI or Python scripts. They can also be created automatically from simulation results saved in VCD files. There are application notes included in the documentation that describe how to create Verilog or VHDL monitors that automatically generate timing diagrams.
The TA has been designed with focus on timing analysis and is much more than just a simple drawing program. Refer to the complete list of features listed on the features page.
Recent poll results indicate there is a small demand for both drawing timing diagrams and performing timing analysis using both the GUI and Python scripts.
No definite conclusions have been reached from the poll results but the list below shows new features and improvements being considered.
- true logic simulation ( simulate then edit )
- improved undo/redo command manager in Python
- internal data structures converted to C++
- GUI converted to wxPython
Comments and feedback are always welcome. Dan Fabrizio firstname.lastname@example.org