Using the TimingAnalyzer, you can quickly and easily draw timing diagrams, build libraries of timing diagrams, and perform timing analysis on logic designs. Setup and hold violations are reported to indicate logic design problems.
Timing diagrams can be created with the GUI, Python scripts, VCD files, and logic simulations. The TimingAnalyzer has been designed with focus on timing analysis but is much more than just a simple drawing program. Check out the complete list of features listed on the features page.
Comments and feedback are always welcome.